“In a multi-channel multiplexed data acquisition system, increasing the number of channels per ADC can improve the overall cost, area, and efficiency of the system. Modern successive approximation register analog-to-digital converters (SAR ADCs) have high throughput and high energy efficiency, enabling system designers to achieve higher channel densities than ever before. This article will show that the setup transient at the input of the multiplexer (caused by a large-scale switching transient at the output of the multiplexer) leads to a longer acquisition time, which significantly reduces the overall throughput of the multi-channel data acquisition system.Then, this article will focus on minimizing input setup time and improving data throughput and system
In a multi-channel multiplexed data acquisition system, increasing the number of channels per ADC can improve the overall cost, area, and efficiency of the system. Modern successive approximation register analog-to-digital converters (SAR ADCs) have high throughput and high energy efficiency, enabling system designers to achieve higher channel densities than ever before. This article will show that the setup transient at the input of the multiplexer (caused by a large-scale switching transient at the output of the multiplexer) leads to a longer acquisition time, which significantly reduces the overall throughput of the multi-channel data acquisition system. Then, this article will focus on the design trade-offs needed to minimize input settling time and increase data throughput and system efficiency.
What is multi-channel DAQ? How to measure the performance of multi-channel DAQ?
The multi-channel data acquisition (DAQ) system is a complete signal chain subsystem that interfaces with multiple inputs (usually sensors). Its main function is to convert the analog signal at the input into digital data that the processing unit can understand. The main components of a multi-channel DAQ system are analog front-end subsystems (buffers, switching elements, and signal conditioning modules), analog-to-digital converters (ADC), and digital interfaces. For high-speed precision converters, switching elements (usually multiplexers) are placed before the ADC driver and the converter itself to take advantage of the advanced performance of modern ADCs. SAR ADC combines high speed and high precision performance and is the most commonly used ADC type for these applications.
High-channel density precision DAQ systems for industrial and medical applications strive to compress the most channels into the smallest possible area. Through the following means, multiplexed DAQ systems can generally achieve high density, high throughput and good energy efficiency:
1. Use high-speed precision SAR ADC
2. Use the lowest sampling rate for each channel
3. Maximize the utilization of SAR ADC converters, among which:
SAR ADC converter utilization
Sampling rate per channel
SAD ADC sampling rate
n is the number of channels. For each converter, the total throughput of the multi-channel data acquisition system is given by:
SAR ADC converter utilization rate × SAR ADC sampling rate
This shows that the total throughput of a multi-channel DAQ system depends not only on the speed and resolution of the SAR ADC, but also on the utilization of this converter.
Figure 1. Block diagram of a typical multiplexed data acquisition system based on SAR ADC
How does latency affect the performance of a multi-channel DAQ system?
In the case of a settling delay, the actual sampling and conversion period of the ADC will increase by a term td, resulting in the actual maximum sampling rate of the converter being given by the following equation:
SRADC, actual, max
Where TADCIt is the sampling period of each sample of the ADC (most ADC data manuals usually provide it, and the more common form is the reciprocal of the SAR ADC sampling rate, in “seconds/sample”). For non-zero delay td, The actual maximum sampling rate of the multi-channel DAQ system is always less than the converter sampling rate, resulting in the converter utilization rate being always lower than 100%. It can be understood that any delay added to the sampling and conversion cycle will reduce the utilization of the converter. When combined with the previous expression about total throughput, the maximum number of channels that a multi-channel DAQ can accommodate will be reduced. In short, any setup delay will reduce the channel density and/or overall throughput of a multi-channel DAQ system.
What are multiplexer input switching glitches and input setup time?
When the multiplexer switches from one input to another input, the output still has the memory of the previous input channel, and its manifestation is the charge stored in the output load capacitance and parasitic drain capacitance of the multiplexer. This is more obvious for high capacitive loads (such as the ADC driver and the ADC itself), because there is no low impedance path for these stored charges. It can even be said that these charges are trapped because the output is capacitive, and modern multiplexers use a break before make (BBM) mechanism, so the multiplexer has high impedance. Only by switching to the next input, these charges can be discharged.
Figure 2. The state before switching (left), after switching, charge sharing occurs, causing a rapid voltage drop by ΔV (right)
After switching, the input capacitance CAWill be connected in parallel to the output capacitor COUT. However, CAAnd COUTMay be at a different potential initially, which will cause CAAnd COUTCharge sharing occurs between. For ultra-high bandwidth multiplexers, charge sharing occurs almost immediately, causing high-frequency glitches at the input of the multiplexer. The amplitude of this glitch, ΔV, is given by:
Where ΔVCIs the difference in capacitor voltage before switching. The transient glitch phenomenon that occurs on the input side of the multiplexer is commonly referred to as kickback, which is more common for switching applications with high capacitive loads (such as ADCs, capacitive DACs, and sampling circuits). This topic has been briefly explained in MT-088. For the converter to generate valid data, the glitch must be stabilized within 1 LSB of the output, and the time required for the input to stabilize within 1 LSB (and stay within this range!) is the input setup time (tS). tSIs the delay t described earlierdIts contribution to this item may be the largest.
When the ADC is not as fast as it is now, these glitches and the corresponding input settling time are insignificant and can be ignored. However, as the ADC speed increases, the converter sampling period becomes shorter and shorter, approaching the magnitude of the input settling time. As mentioned earlier, when the ADC period TADCEqual to the input setup time tS(Actually td), the converter utilization rate is greatly reduced to 50%. This means that we only used half the power of the converter! It is necessary to reiterate the importance of input settling time, which should be developed simultaneously with the current technology of precision converters, paving the way for improving the performance of multi-channel DAQ systems.
How to minimize the input setup time?
To minimize switching glitches, an RC filter (refer to CN-0292) is usually used between the buffer amplifier and the multiplexer, which is called a buffer network. Figure 3 shows the signal chain subsystem of a dual-channel multiplexed analog front-end subsystem and its corresponding switch timing diagram.
Figure 3. The dual-channel multiplexed analog front-end subsystem of the multi-channel DAQ system and the corresponding timing diagram
The buffer RC is the dominant pole. Assuming that the multiplexer has a very high bandwidth relative to the amplifier and buffer RC, the input glitch and set-up transient can be approximated as having a first-order (exponential) response. To further analyze the input glitch, Figure 4 shows the input glitch transient response in detail.
For the first-order hypothesis, the error VERRORThe expression of is a decreasing exponential function of time. VERRORThe initial value (the value at the time of switching) is the glitch amplitude ΔV, which will decay at a rate determined by the buffer RC value. VERRORThe time required to stabilize within 1 LSB is defined as the input settling time.
Figure 4. Analysis of multiplexer input glitches during switching: timing definition and design goals
On the other hand, the converter takes the period tACQSampling (also called acquisition time). At tACQAfter the ADC conversion phase has passed, the converter will quantify any available sampled data. If vERRORThe decay speed is too slow, causing it to not stabilize within a certain value (1 LSB to a few LSB), which will cause problems. This will cause the current sample to be corrupted by the previous analog input, causing crosstalk between ADC channels. Taking into account the input settling time, it must be ensured that the input settling time is less than the acquisition time of the converter to minimize the error. Moreover, to further reduce tSIt also provides an opportunity to use faster converters to increase overall system throughput and density.
Use our mathematical skills when ΔVCIs the full-scale input range and VERRORWhen at least 1 LSB is reached (the multiplexer output is within 1 LSB of the target level), an expression for the fastest input settling time in the worst case can be derived. Designers of multi-channel DAQ systems will have two design tools: buffer time constant and CA/COUTRatio, which gives an expression for the input settling time:
It can be seen here that the input settling time is the buffer time constant τ and VERRORA linear function of the number of time constants η required to stabilize within 1 LSB. The most straightforward way to reduce the input settling time is to use a buffer network with a smaller time constant, which makes sense because a faster (high bandwidth) buffer network will reduce the time constant. However, this approach will introduce a different set of trade-offs involving noise and load. On the other hand, minimizing the η term can also achieve similar results.
η is the snubber capacitance (CA) And output capacitance (COUT) As a function of the ratio. If 1 LSB is equal to the full-scale input range divided by the N-1 power of 2 (N is the number of bits), and in the worst case ΔVCEqual to the full-scale input range, the expression can be further simplified.
Equation 6 may not be so intuitive and difficult to visualize, so it may be better to use only semi-logarithmic graphs with 10-bit, 14-bit, 18-bit, and 20-bit resolution, as shown in Figure 5.
Figure 5. Graph of the time constant required to establish to 1 LSB
It can be seen that CA/COUTThe higher the value, the shorter the settling time; when the capacitance ratio is very high, the settling time is even close to zero. COUTIt is essentially the drain capacitance of the multiplexer and the input capacitance of the subsequent stages, so there is only CAMaintain a more flexible degree of freedom. For 10-bit resolution, to make the settling time 0, CASubi COUTAt least 1000 times larger; for a 20-bit system, at least larger than COUT1,000,000 times bigger! For example, for 10-bit and 20-bit systems, in order to make the settling time 0, a typical load of 100 pF requires 100 nF and 100 μF snubber capacitors, respectively.
In short, minimizing input settling time can be achieved in two ways:
1. Use high bandwidth for the buffer network
2. Relative to COUT, Use higher CAvalue.
High bandwidth and large buffer capacitance can minimize the input settling time, so just use the highest bandwidth and largest capacitance
No! The RC load effect and the drive capability of the amplifier must be considered! In order to study the impact of the buffer network on the load of the buffer amplifier, the analog front-end subsystem should be analyzed in the frequency domain.
Since we base the input glitch on the idea of first-order response, the pole of the buffer network should be the most important contributor. In other words, the buffer bandwidth should be smaller than the bandwidth of the buffer amplifier and multiplexer to avoid multi-pole interaction and ensure that the first-order approximation holds.
Figure 6. Buffer and buffer equivalent circuit (left) and the equivalent impedance of the amplifier and buffer network (right)
A typical buffer architecture consists of a cascade of precision amplifiers configured with a buffer (G = 1) and a buffer network. Analyzed in the frequency domain, the output of this subsystem depends on the ratio of the buffer input impedance to the sum of the buffer input impedance and the amplifier’s closed-loop output impedance. The inspection shows that in order to avoid the load effect, the input impedance of the buffer should be greater than the closed-loop impedance of the amplifier, as shown in Equation 7.
In other words, in order to prevent the buffer network from becoming the load of the buffer amplifier, we should:
1. Increase the buffer time constant RACATo effectively reduce bandwidth
2. Use a smaller snubber capacitor CA
3. Choose an amplifier with a very low closed-loop output impedance
The first two options give us a clear understanding of the trade-off between load effect and input settling time. This limits the buffer bandwidth and the size of the capacitance that we can use. The third option introduces a performance parameter that should be considered when selecting the appropriate precision amplifier. Stability and driving ability should also be considered.
Figure 7 shows that for a precision amplifier with sufficient bandwidth (for example, ADA4096-2 with a -3 dB closed-loop bandwidth of approximately 970 kHz), the results are consistent with the current analysis, except for a few waveforms. For a buffer bandwidth of 10 kHz, the maximum CAProduce the fastest input setup time. For a buffer bandwidth of 200 kHz, increase CAIt will still speed up the settling time until the load effect occurs. The underdamped response seen from the results has a very small glitch amplitude, but the settling time is relatively small. CAThe resulting response is longer, although the latter has a higher glitch amplitude. This highlights the importance of carefully studying how the buffer loads the amplifier, which must be considered when selecting devices for the system.
Figure 7. Multiplexer input for 10 kHz (top) and 200 kHz (bottom) buffer bandwidths, ADA4096-2 amplifier model
As mentioned earlier, one amplifier parameter that needs attention is the closed-loop output impedance. The closed-loop impedance of an operational amplifier is usually its open-loop gain AVInversely proportional. We also hope that the buffer network has a high bandwidth to minimize the settling time, so the -3 dB bandwidth of the amplifier is required to be even greater than the buffer bandwidth. In addition to lower noise, offset and offset drift, the most suitable precision amplifier for multiplexed DAQ systems to achieve minimum input settling time has two priority characteristics: 1) High bandwidth, 2) Very low Closed loop impedance. However, these advantages are not without cost, and the cost is in the form of power consumption. For example, we can view the closed-loop impedance of the ADA4096-2 and ADA4522-2 shown in Figure 8.
Figure 8a. Closed-loop impedance diagram in the ADA4522-2 data sheet
Figure 8b. Closed-loop impedance diagram in the ADA4096-2 data sheet
Considering the closed-loop output impedance diagram in the data sheet and the -3 dB closed-loop bandwidth of the ADA4522-2 of 6 MHz (nominal value), it is obvious that it is a more suitable driver for this application. But when power consumption is prioritized, the power supply current of each amplifier of the ADA4096-2 is 60 μA (typical value), which is more attractive than the 830 μA (typical value) of each amplifier of the ADA4522-2. Nevertheless, both precision amplifiers can be used, ultimately depending on what the application really needs to achieve.
How do we do the best?
To maximize the density and throughput of a multi-channel DAQ system, the input settling time should be less than or equal to the ADC acquisition time. Any additional delay will degrade the performance of the multi-channel DAQ system. In order to minimize the input settling time, the bandwidth and capacitance of the buffer network need to be increased, but care must be taken when selecting component values to avoid load effects in the frequency domain. Finally, choosing the most suitable precision amplifier requires balancing power consumption, closed-loop output impedance and -3 dB bandwidth, and determining its priority according to the real needs of the application.
Corrigan, T. Application note, how to calculate the settling time and sampling rate of a multiplexer. Analog Devices, 2009.
Interactive design tool: analog switch setup time calculator. ADI company.
MT-088, basic knowledge of analog switches and multiplexers. Analog Devices, 2009.
Dan Burton, Vicky Wong, Peter Ohlon, Eric Carty, Rob Kiely, May Porley, Jess Espiritu, Jof Santillan, Patrice Legaspi, Peter Hurrell, and Sherwin Almazan.
Dan Burton, Vicky Wong, Peter Ohlon, Eric Carty, Rob Kiely, May Porley, Jess Espiritu, Jof Santillan, Patrice Legaspi, Peter Hurrell and Sherwin Almazan.
Joseph Leandro Peje [[email protected]