“The outstanding feature of the embedded dingye control system is the anti-interference and reliable stability under the environment of high and low temperature and high electromagnetic radiation. compared to PLC systems. Its obvious advantages are fast processing speed, easy to set up industrial Ethernet, convenient programming, good versatility, and the price is only a fraction of the PLC, which has a good development prospect. This paper mainly discusses the design of the embedded I/O system with EP9315 and MAX2_EPM240 as the core.
Introduction: The outstanding features of the embedded Dingye control system are the anti-interference and reliable stability under the environment of high and low temperature and high electromagnetic radiation. compared to PLC systems. Its obvious advantages are fast processing speed, easy to set up industrial Ethernet, convenient programming, good versatility, and the price is only a fraction of the PLC, which has a good development prospect. This paper mainly discusses the design of the embedded I/O system with EP9315 and MAX2_EPM240 as the core.
1 System Configuration
The whole embedded input and output system is divided into three parts: embedded system, application module (ie input and output module) and conversion module. The overall structure is shown in Figure 1.
Figure 1 System structure block diagram
1.1 Embedded System
This design selects the high-performance ARM9 embedded microprocessor EP9315 of CirrusLogic Company. This microprocessor has all the excellent performance of ARM920T core. The rich integrated peripheral interface includes Ethernet MAC, serial port, 2.0 full-speed HOSTUSB, LCD interface with dedicated SDRAM channel, touch screen interface, etc.
Cirrus logic company provides users with a full-featured development board based on this processor. Cooperate with Windows CE. net embedded operating system, with high system development efficiency and stable operation, provides a reliable system platform for industrial control. Based on the customized WinCE operating system, the special driver of the application module in the industrial control is realized, and the generality of the embedded system is improved.
The system described in this paper uses the rich integrated peripheral interface of the development board. Download eboot through serial port; download operating system kernel and application program through Ethernet, and realize Ethernet communication; HOST USB is connected to mouse to facilitate user operation; LCD screen realizes Display, and touch screen interface realizes panel touch operation.
1.2 Design of the conversion module
The conversion module is used to lead out the signal lines that need to be used on the development board, mainly including data lines, address lines and some I/O control signals (such as nWR, nRD, NCS3, nWAIT, etc.). The level conversion driver chip 74LVXC4245 is mainly used in the conversion module, and its functions include: (1) improving the quality of the signal; (2) anti-interference; (3) realizing level conversion; (4) improving the driving capability of the EP9315 pin .
1.3 Design of input and output module based on CPLD
1.3.1 Design idea of input and output module
In industrial applications, input/output modules usually include digital input modules, digital output modules, digital input/output modules, analog input modules, analog output modules, and analog input/output modules.
Considering that the complexity of different application systems is different, the requirements for input and output ports are also different. In order to flexibly add different types of input and output modules according to actual needs, the following ideas are adopted in the design:
The data bus, address bus and control bus of ARM9 are connected to multiple slots at the same time, and each slot is given a fixed address, called slot address, and various modules can be inserted into any slot.
All kinds of input/output modules are developed and designed based on CPLD, to realize the detection and control of the external system. But for different input and output application systems, the input signal and output signal characteristics are different, showing complexity. The above-mentioned complexity must be considered in the design, and the corresponding input and output signals must be signal-conditioned according to the actual situation. In order to ensure the stability and speed of the connection between the input and output modules and the ARM9 master controller, the expansion of the bus method is adopted: the CPLD is hung in the BANK3 space of the ARM9, and 11 address lines, 16 data lines, and corresponding control lines are connected. (including nRD, nWR, nCS3, nWAIT). The overall design block diagram of various input/output modules can be shown in Figure 2.
Figure 2 Block diagram of the input and output module structure
The main functions of the signal conditioning circuit are: realize the conditioning of various input signals to meet the electrical requirements of the CPLD input pins; realize the conditioning of the CPLD output signals to meet the electrical requirements of the application system. CPLD bus function: establish the signal connection between CPLD and ARM9 through various buses to realize the communication between CPLD and ARM9.
Because various types of modules can be inserted into any slot, in order to realize the automatic identification of different types of modules, each type of module is given an ID code through the hardware design language. ARM can determine what kind of module it is by reading the ID code through the “read ID code address”. The corresponding operation can then be carried out according to the module type.
1.3.2 Selected port data of CPLD.
Altera’s MAXII device adopts a new CPLD structure, which is more cost-effective, lower power consumption, and larger capacity than previous MAX devices, making it an ideal solution for complex control applications. Considering that the functions of the input and output modules are relatively simple and do not require a large number of complex operations, the system is designed with a relatively small capacity EPM240.
1.3.3 Software Design of CPLD
In order to realize the read and write control of the input and output module through the address bus, data bus and control bus of ARM9, the CPLD of the input and output module must be programmed in hardware language according to the read and write sequence diagram of ARM9.
The key code of the input module is as follows:
The function of the first assign statement in the program: when the lower five bits of the address bus are 5’b00000, which is the “read module ID code address”, the module’s ID code is output to the data bus.
The function of the second assign statement: when the lower five bits of the address bus are 5″b00100, that is, “read module data address”, the module input port data is read into the data bus.
The simulation result of the input module Quatuttis II is shown in Figure 3. As can be seen from the figure, when the lower five-bit address of the address bus is 5’b00100, the module input port data (de24v_in) is read into the data bus (data_bus).
Figure 3 Input module simulation timing diagram
In the same way, the tank module design can be carried out, and the key code is as follows:
always @ (posedge pro_clk) begin
mem_data[ i ]=data_bus;
if((mem data ==mem_data)&(mem_data==mem_data)&(mem_data==
relay_reg = mem_data;
assign relay = relay_reg;
assign led = ~relay_reg;
assign data_bus = ((~(RDICS))&(address==baddr[10:5])&(baddr[4:0]==5’b00000))?16’b0000000011011110:16’bz;
The function of the alwavs statement in the program: when the lower five bits of the address bus are 5’b00010, which is the “write module data address”, the data bus data is written to the register mem_data. In order to enhance the anti-interference ability, the program adopts continuous reading of the data bus data four times and judges whether it is consistent. If it is consistent, the module output port data is updated.
The function of the third assign statement in the program: when the lower five bits of the address bus are 5’b00000, which is the “read module ID code address”, the module’s ID code is output to the data bus.
Output module Quarutu. The simulation result of II is shown in Fig. 4. As can be seen from the figure, when the lower five bits of the address bus are 5’b00100, the data bus (data_bus) is written to the module output port (relay).
Figure 4 Output module simulation timing diagram
2 System software design
2.1 Driver Design Ideas
The I/O module driver is designed based on the stream interface driver type. The design of the driver should consider the reasonable allocation of physical addresses according to the realization function on the one hand, and the interface with the application program on the other hand. The following is a detailed discussion of the design ideas of the driver around these two aspects.
2.1.1 Reasonable allocation of physical addresses
For the input module, the following two operations are included. (1) Read the ID code; (2) Read the input port data. For the output module, the following two operations are included. (1) Read ID code; (2) Write data to the output port.
In order to ensure the universality of the driver, that is to say, for the module inserted into a certain slot, whether it is an input module or an output module, the driver structure is the same. Three physical addresses can be assigned to each slot, including reading the ID code address (referred to as “ID address”), reading the input module data address (referred to as “read address”), and writing data to the output module address (referred to as “” write address”). The application program judges the type of the module through the ID code data read by the “ID address”, and then reads the input module through the “read address”, or writes the output module through the “write address”. The read and write operations to the input and output modules include word operations, byte operations, and bit operations, which can be implemented in the driver program through the “AND operation and shift operation” transformation. For each slot, three physical addresses can be assigned as shown in Table 1:
Table 1 Application module physical address allocation
In the initialization function (IO_Init), through the functions VirtualAlloc() and VirtualCopy(), the physical address of the EP9315 module for input/output is linked with the virtual space of the operating system to realize address mapping.
2.1.2 Implementation of read and write operations of input and output modules
The application flow of operating the input and output modules can be briefly described as follows: Send “read module ID command code” -> receive the data returned by the driver (ie module ID code) -> judge the module type (input module or output module) according to the module ID code -> send the relevant command code according to the function of the module to carry out the module Read operation or write operation (including word operation, byte operation and bit operation).
The driver design idea is as follows: the function implemented in the write function (IO_WRITE) is: accept the command code, and store the command code in a specified variable; judge whether the command code is a write command code; if so, execute the write operation (including word operation, Byte operation and bit operation three cases). The function implemented in the read function (IO_READ) is: judging whether the command code is a read command code, if so, execute the read operation and return the read data (including word operation, byte operation and bit operation).
2.1.3 Adjustment of input and output module read and write pulse width
Under the WinCE operating system, the main frequency of EP9315 reaches 200MHz, the bus frequency is 100MHz, and the peripheral clock is 50MHz. Therefore, the pulse width of the read-write and enable signals sent by EP9315 is less than 50ns. You can change the read and write timing on BANK3 of EP9315. It can interact with CPLD. Specifically, it can be realized by setting the waiting time bits WST1 and WST2 in the storage space of the application module address space to read and write the characteristic register SMCBCR3.
If the code of SMCBCR3 is set as: SMCBCR3=2000ffef, the realized function is: set the nCS3 data width to 32bits, and the read and write pulse width to 320ns. This setting makes the CPLD have a lower bus frequency and meets the read and write timing requirements for the CPLD.
The author’s innovation is based on the MAX2_EPM240 hardware and software design of the input and output modules, in Windows CE. NET operating system, the EP9315 embedded system controls the input and output modules, and various modules can be flexibly selected according to actual needs. The system has low power consumption and good stability, and is suitable for use in industrial control.