Center-Aligned SVPWM Implementation of a 3-Phase 3-Level Inverter

Summary

Space Vector Pulse Width Modulation (SVPWM) is widely used in 3-phase inverter control systems. The most efficient method for SVPWM MCU implementation is center-aligned PWM because the PWM module in the MCU can easily generate center-aligned PWM. This article will discuss SVPWM implementation methods and introduce an easy method to implement center-aligned SVPWM, which is suitable for on-chip PWM modules.

1 introduction

SVPWM is widely used in 3-phase inverter control systems because it has higher DC side voltage utilization efficiency than sinusoidal pulse width modulation (SPWM). Although SVPWM has many advantages, it is difficult to implement. The hardest factor is calculating the duty cycle of each power switch, as well as determining the vector sector and pulse train for each switching cycle. Many articles describe the duty cycle calculation method for a 3-phase 2-level inverter, and there are many methods that we can use to calculate the vector sequence (for example, the center-aligned method, which can be easily implemented in MCU platforms).

In order to improve the system efficiency of 3-phase inverters, 3-level or multi-level inverters are becoming more and more popular. A 3-level inverter has more power switches (up to 12) than a 2-level inverter; this means that a 3-level inverter has more vector sectors than a 2-level inverter . Therefore, compared to the 2-level inverter, the duty cycle calculation and vector calculation of the 3-level inverter SVPWM are more complicated.

This article[1]A simple method for calculating vector sectors is introduced. There are only 2 steps in the calculation process. Step 1 divides the entire vector into 6 main sectors. This step is very similar to the sector calculation method for a 2-level inverter. In step 2, the reference sector is relocated into one of the 6 sectors, and then the main sector is divided into 6 sub-sectors. This calculation method can be used for a 2-level inverter to determine the effective vector and calculate its dwell time. However, we have not discussed the vector sequence for each switching cycle, and the duty cycle calculation method is difficult to implement in MCU applications.This article[2]Use the same method for computing vectors. The repositioned zero vector is used as the zero vector of the 2-level inverter, and the resulting vector sequence is the same as that of the 2-level inverter. In the implementation process, the MCU is used to generate the sequence signals and the peripheral logic circuit is used for the realized PWM generation of each power switch. We have not introduced a method that does not have peripheral logic circuits and is suitable for MCU implementation.

The most efficient method for SVPWM MCU implementation is center-aligned PWM, because the MCU’s PWM module can easily generate center-aligned PWM.This article will be based on[1]and[2]The method, discusses SVPWM implementation, and introduces a simple method to implement center-aligned SVPWM, which is suitable for an on-chip PWM module.

2 3Mutually3The basics of a stage inverterSVPWMprinciple

Figure 1 shows the hardware topology of a neutral point clamp (NPC) type 3-phase 3-level inverter.

picture1NPC 3Mutually3Hardware topology of stage inverter

In Figure 1, there are 3 NPC legs (R, S, and T); each leg includes 4 power switches. The 4 power switches for each leg must be controlled in two compensated pairs. Qx1, Qx3 (x = R, S, T) are one compensation pair, and Qx2, Qx4 are the other pair. Therefore, for each leg, it can output 3 different phase voltage states through 4 power switches.

surface1Output status of each leg

There are 27 states when controlling the power switch of each leg (see Table 1); each state can be mapped to an α-β coordinate plane vector diagram. 27 vectors can form 18 sectors, as shown in Figure 2.

picture2 3Mutually3stage inverterSVPWMvector

Suppose the reference vector Vref. According to SVPWM theory, we have to find the two closest vectors V in Figure 2xVyand a zero vector Vzto form the vector Vref. Figure 2 shows that Vrefand VxVyVzThe relationship between. Therefore, we can choose the vector PNN (Vx), PNN (Vy) and NNN (Vz), forming Vref. If the interval T is specifiedsInner VxVyVzThe pause times are TxTyTzthe following function can be obtained:

However, it is difficult to determine Vx, Vy, Vz just by the angles used in 2-level SVPWM, because even if the angles are the same, the reference vectors can be located in different sectors. In order to determine the sector, the size of the reference vector is required, but it increases the complexity of the calculation method.

[1]and[2]A simple method to calculate Vx, Vy, Vz is introduced. First, the entire vector diagram shown in Figure 2 is divided into 6 main sectors. Each main sector contains 10 original sectors, which form a sub-hexagon. The 6 main sectors are continuously distributed with an angular difference of 60 degrees. Figure 3 shows the 6 main sectors.

picture33classSVPWMmain sector of

Given the reference vector Vref, the main sector can be calculated using only this angle. For example, in FIG. 4 , the angle θ between Vref and the α axis is +60 degrees to -60 degrees, which means that the Vref main sector is sector 1 .

picture4main sector1

After calculating the main sector, it must map the initial vector into the selected main sector. The mapping algorithm is as follows:

For example, the initial vectors of primary sector 1 are PPP(OOO, NNN), POP(NON), PNO, PNN, PON, PPO(OON), POO(ONN). To obtain a hexagon similar to a 2-level SVPWM, take POO(ONN) as the mapping vector Vmap1=V0. After mapping, we can get the hexagon shown in Figure 5, which is the same as the vector diagram of the 2-level SVPWM. In this hexagon, there are a total of 7 mapping vectors, which form 6 sub-sectors in the hexagon.

picture5 main sector1map

From Figure 5, we can see that Vref is located in sub-sector 1, and we can easily calculate the pause vector as.Can be used as zero vector for 2-level SVPWM. Therefore, we can get the following function:

Combining equation (2) and equation (3), we get:

therefore

From Equation 4, if the dwell time can be calculatedand, the initial vector pause time can be calculated. Mapped by Figure 5, the vector selection and dwell time calculation of 3-level SVPWM is completely converted to 2-level SVPWM. Different main sectors have different mapping vectors. Table 2 summarizes the mapping vector for each main sector.

surface2 Mapping vector for each main sector

3 Simple way to calculate main sector

Using the angle of the α-β coordinate plane Vref, the main sector can be calculated. As shown in Figures 2 and 3, each main sector is located within a fixed angular range.For example, the angular range of the first main sector is.The angular extent of the second main sector can also be calculated as. Therefore, the overlapping area between the first and second main sectors extends to two adjacent areas. These overlapping regions increase the computational difficulty of the main sector. In order to specify the exclusive angular area of ​​each sector, we can redefine the main sector, as shown in Figure 6.

picture6 New definition of main sector

Using the definition shown in Figure 6, each main sector has its own angular area and its own sub-sectors.

Given the 3-phase voltage waveform shown in Figure 7, the corresponding main sector is marked in the correct position. From Figure 7, Table 3 summarizes the relationship between the main sector number and the 3 phase elements, which can help to easily determine the main sector.

picture7 main sector location

surface3 Primary sector determination method

4 sub-sector process

In a 2-level SVPWM, the first step is to find the sector number that determines the stall vector. The second step is to calculate the dwell time for each selected vector. According to the 3-level SVPWM principle in Chapter 1, when the main sector is determined and all vectors are mapped to the main sector, the same process as the 2-level SVPWM can be used to determine the sub-sectors and calculate the dwell time for each stall vector . This process algorithm has been introduced in many articles, so this paper will not discuss the sub-sector determination method and the dwell time calculation method.

Although we can find out the dwell time of each vector by the sub-sector method, the duty cycle distribution of each power switch is much more complicated than 2-level SVPWM. The 3-level SVPWM has 6 pairs of compensated power switches, which means that when we get the dwell time of the selected vector, 6 duty values ​​must be calculated. To simplify the duty cycle calculation process, this article presents an efficient method for easily calculating the duty cycle of each pair of power switches.

We also use main sector 1 as an example. According to Figure 4, the R phase has no N state. In addition to this, if OON, ONO and OOO are selected for vector mapping, the S and T phases have no P states. For the R phase, replace the P state with a 1 and replace the O state with a 0. For the S and T phases, the O state is replaced by a 1 and the N state is replaced by a 0. The result is the same vector diagram as 2-level SVPWM. Figure 8 shows this operation.

After completing the 2-level SVPWM process, the pauses of the 3 vectors are known. As shown in Figure 8, Tx is 100 pause times, Ty is 110 pause times, and Tz is 111 and 000 pause times. Therefore, we can use the center-aligned PWM output mode to calculate the 3 duty cycles (d1, d2 and d3) of the 3 pairs of compensated power switches; the resulting vector sequence in this example is 000→100→110→111→110→100→ 000. The left side of Figure 9 shows the state of the upper-level switches of the three pairs of compensation power switches in the 2-level SVPWM, which is called center-aligned SVPWM.

picture9 2Stage Inverter Center AlignedSVPWM

If we replace 1 and 0 with P and N, respectively, we get the right part of the 3-level inverter center-aligned SVPWM. The vector sequence for 3-level SVPWM is:

ONN→PNN→PON→POO→PON→PNN→ONN.

The positive power switch pair is Qx1 and Qx3 (x = R, S, T); the negative power switch pair is Qx4 and Qx2 (x = R, S, T). Our definition of each pair of states 0 and 1 is also the same as for 2-level SVPWM. Therefore, for main sector 1, within a single switching cycle, the negative R phase pair is always 0, and for the S, T phases, the positive pair is always 0. Then, only 3 pairs of power switches must be controlled by different duty ratios, positive R phase pairs and negative S, T phase pairs, which are equivalent to 3 pairs of power switches of 2-level SVPWM. This means that in main sector 1, d1 can be assigned to a positive R phase pair, d2 can be assigned to a negative S phase pair, and d3 can be assigned to a negative T phase pair.

The previous analysis results can be extended to other vectors. Table 4 summarizes the status substitution, and Table 5 lists the duty cycle assignments for each main sector.

surface4 The status of each main sector is replaced by

surface5 Duty cycle assignment for each main sector

5 Algorithm implementation

From the analysis in Section 4, we can implement a 3-level SVPWM algorithm. Figure 10 shows the software flow chart.

picture10 3classSVPWMAlgorithm flowchart

In Figure 10, all function inputs are the αβ elements of the reference vector.

RevParkConv is the function of the reverse transformation of Park, from which we can get 3 phase static elements.

MainSectorCal is a function that determines the main sector number from the results listed in Table 3.

MapVector is a function that maps the datum vector to the selected main sector. Table 2 lists the elements of the mapping vector αβ.

Svgen_dq_2_Level is a function that implements the 2-level SVPWM process, from which we can know the three duty ratios d1, d2 and d3.

DutyAssign is a function of assigning a CMPR value to a power switch pair using the results listed in Table 5.

6 Simulation results

To test the effectiveness of the algorithms discussed in Chapter 5, we use the Matlab Simulink Platform to obtain simulation results. All algorithms are done through C code s-functions, which can be easily ported to real-world systems.

The simulation conditions are as follows:

. Three-phase three-level NPC bridge

. Switching frequency: 10kHz, PWM cycle count: 3000

. DC side voltage: 700V

. Reference phase-to-phase voltage: (1) 200 V/50 Hz; (2) 280 V/50 Hz

. LC filter parameters: each phase, L=9mH, C=4.7μf

. R load: 100Ω per phase

picture11Simulation results

(CH1:The reference voltage;CH2:The output voltage;CH3: main sector calculation;CH4: Sub-sector calculation)

picture12 Simulation results

(CH1: Positive QR1 PWM; CH2: Negative QS2 PWM; CH3: Negative QT2 PWM; CH4: Main Sector)

picture13 220VacoutputCMPRvalue

CH1:RPhase positive (blue) and negative (green)CMPRvalue

CH2:SPhase positive (blue) and negative (green)CMPRvalue

CH3:TPhase positive (blue) and negative (green)CMPRvalue

CH4: main sector

picture14 280VacoutputCMPRvalue

CH1:RPhase positive (blue) and negative (green)CMPRvalue

CH2:SPhase positive (blue) and negative (green)CMPRvalue

CH3:TPhase positive (blue) and negative (green)CMPRvalue

CH4: main sector

From the simulation results shown in Figure 11-Figure 14, it has been proved that the algorithm is correct. This algorithm can be used to implement 3-level 3-phase inverter SVPWM. However, further research is required because the dead time and the effects of voltage imbalance on the DC side are not taken into account. Therefore, we must pay special attention to the limitations of this method.

references

1. “Synchronous and symmetrical waveform three-level VSI improved SVPWM algorithm”, author: Abdul RahimanBeig, IEEE members G.NaraYanan, G.NaraYanan and IEEE senior member VTRanganathan.

2. “New Simple Space Vector PWM Method for Three-Level Inverter”, by IEEE members Jae HyeongSeo, Chang Ho Choi and IEEE senior member Dong Seok Hyun.

3. “Single-phase three-level NPC inverter new SVPWM method and neutral point voltage balance control method”.

4. Guangzhou, Guangdong, China (510640) Zhang Zhi, Xie Yun-xiang, Huang Wei-ping, Le Jiang-yuan and Chen Lin, Southern University of Science and Technology of China.