Arasan announces first ONFI v5.0 compliant NAND Flash IP

Arasan announces first ONFI v5.0 compliant NAND Flash IP

Arasan announces first ONFI v5.0 compliant NAND Flash IP

Arasan Chip Systems is making available their Total IP Solution for Nand Flash compliant to the Open Nand Flash Interface (ONFI) 5.0 Specification.

The company, a provider of Semiconductor IP for the Internet of Things (IoT), mobile and automobile SoCs, said that its Total IP for ONFI v5.0 NAND Flash includes the Host controller IP, PHY IP and software stack. The ONFI 5.0 Standard is 50% faster than the previous ONFI 4.2 standard. The ONFI Test Chip is available on 12nm.

According to Arasan, the NAND Flash Controller IP enables simple, dependable access to off-chip NAND flash devices at much faster speeds. The updated controller supports all ONFI Specification modes at all speeds, which includes the new NV-LPDDR4 mode, in addition to the legacy Single Data Rate (asynchronous), NV-DDR (synchronous), NV-DDR2, and NV-DDR3 double data rate modes.

It supports all timing modes for these interface modes, from the low 10MHz mode up to the brand new 1,200MHz (2.4GT/S) I/O speeds. The Arasan’s ONFI 5.0 Host controller IP is the first in Arasan’s ONFI host controller line to have a fully verified AXI interface. It comprises unique microcontroller architecture, to make sure every ONFI data path is fully utilised in a multithreaded fashion.

The Arasan’s ONFI 5.0 Host controller IP also features a full Scatter gather Direct Memory Access (DMA) algorithm that is capable of moving from the flash to system memory at speeds matching the speed of the flash interface

The ONFI 5.0 PHY IP is designed to connect seamlessly with the company’s ONFI 5.0 Host Controller IP. Arasan’s ONFI 5.0 PHY has complete SDR, NV-DDR, NV-DDR2, NV-DDR3 and NV-LPDDR4 TX/RX functionality and supports all the speeds defined in the ONFI specification while remaining backwards compatible with the prior versions of the ONFI specifications.

The ONFI 5.0 PHY has been designed to enable data training, various power drives and ZQ calibration, which ensures maximum operating speed and optimum signal integrity. The PHY uses a PLL / DLL combination to provide very flexible frequency access. It also includes ESD protection on all of the various ONFI interface pins.

The ONFI 5.0 NAND Flash Controller IP and PHY are available to license immediately. The PHY is available on nodes 12nm and below.

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