24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system

Circuit functions and advantages
The circuit shown in Figure 1 provides a high dynamic range 4-channel simultaneous sampling system with high crosstalk isolation and flexible sampling rates, requires minimal external components, and can be easily interfaced to a DSP or FPGA. The circuit’s four sigma-delta ADCAD7765s are daisy-chained so the number of connections to the digital host is minimized. The AD7765 fully integrates differential input/output amplifiers and reference buffers, significantly reducing the number of external components required.

Using the AD7765 in a simultaneous sampling configuration provides the following advantages:

• Inter-channel crosstalk isolation is better than a single-chip solution that integrates multiple 24-bit ADCs.
• 112 dB dynamic range at 156 kSPS.
• Support for more or less number of channels.
• Supports multiple SYNC controls (which can be phase-shifted with respect to each other).
• Double decimation rates (128 and 256) and flexible sampling clocks can handle a wide range of input bandwidths.

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Figure 1. Four AD7765 ADCs Daisy-Chained for Simultaneous Sampling (Simplified Schematic, Decoupling and All Connections Not Shown)

circuit description
Each AD7765 is clocked by a common sampling clock (MCLK), synchronization signal (SYNC), and reset signal (RESET), as shown in Figure 1. The 4.096 V common reference provided by the ADR444 (using the circuit shown in Figure 5) is applied to each AD7765 in a single-point star configuration (reference buffers built into each ADC).

A RESET pulse is applied to all devices on power-up (the minimum low time of the pulse is 1 × MCLK period). The rising edge of RESET (which takes the ADC out of reset) is applied to each AD7765 to synchronize with the falling edge of MCLK. A SYNC pulse (minimum low time of 4 × MCLK periods) is then applied to all AD7765 devices, which gates the AD7765’s digital filter when it is logic low. On the first MCLK falling edge after SYNC returns to logic high, the digital filter of the AD7765 begins processing samples internally.

The SYNC function plays the following two roles:
1. Provide discrete points in time for each AD7765 to begin processing sampling.
2. Ensure that the data output of the SDO pin of each device is synchronized (the FSO falling edge of each ADC is synchronized), as shown in Figure 2.

Once all devices are synchronized, all ADCs can be configured. The daisy-chain mode of operation requires all ADCs to use the same decimation rate (controlled by pin 18) and power mode (controlled by writing to the control register address 0x0001) settings, thus ensuring that data is output from each device synchronously.

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Figure 2. Oscilloscope plot of the FSO of each AD7765 channel, with simultaneous sampling zoomed in at an output data rate of 156 kSPS

In order to write to all four devices in the daisy chain, a common FSI (frame sync input) signal is applied to all AD7765s. A write operation to the AD7765 consists of 32 bits (16 address bits, 16 register bits). FSI transfers data to the device in frames. When writing to all four devices, the SDI input of the daisy chain is loaded with a single data write instruction, that is, when FSI goes low, 32 bits of data are written to the SDI (serial data input) of the AD7765 (4).

The example in this note operates in normal power mode with a decimation factor of 128 (maximum output data rate of 156 kSPS).

Read data from the daisy chain
Only one FSO (Frame Sync Out) signal is applied to the digital host as an interrupt to read data from the daisy chain (FSO (1)). This signal is the frame signal for all four channels. The data format read back from the digital host (FPGA or DSP) is shown in Figure 3. The conversion data and status bits of the AD7765 (1) are output first (during which FSO (1) is active low), followed by the conversion data and status bits of the AD7765 (2), (3), (4). Note that FSO(1) is logic high when outputting data results from the remaining converters in the daisy chain.

The next time FSO(1) transitions from logic high to logic low, the next set of samples for all four channels is available for readback. The digital master needs to start readback on the falling edge of FSO (1) and read back 4 × 32 bits, or 128 bits, from the SDO (1) serial output. The data output on SDO (serial data output) is synchronized with SCO (serial clock output).

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Figure 3. Daisy chain: read data. Digital interface from AD7765 (1) to FPGA. The data of each channel is represented by color and number.Output data rate of 156 kSPS (1/128 decimation) amplification

performance
 
The AD7765 daisy-chain circuit allows the user to simultaneously sample up to 4 channels at an output data rate of 156 kSPS. The output data rate can be changed by reducing the MCLK frequency or changing the decimation rate of the AD7765. After changing the decimation rate, it is recommended to resynchronize these ADCs. Figure 4 shows the output FFT of the AD7765 (3) operating at a maximum sampling rate of 156 kSPS and an MCLK frequency of 40 MHz. A −0.5 dBFS input signal is applied to the differential amplifier input of the AD7765 at a 1 kHz input frequency.

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Figure 4. FFT Output for 1 kH Input Signal: 156 kSPS Sample Rate, 40 MHz MCLK, 100 μF Reference Star Single Point Capacitor, 131,072 Samples

Figure 5 shows the output FFT of the AD7765 (3) operating at a sampling rate of 97.65 kSPS, an MCLK frequency of 25 MHz, and an input signal of 1 kHz (−0.5 dBFS). Table 1 lists the performance of the AD7765 at 40 MHz, 30 MHz, 25 MHz, 20 MHz, and normal power modes.

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Table 1. Performance vs. Reference Star Single-Point Capacitor. AD7765 with 1/128 decimation rate, normal power mode, −0.5 dBFS 1 kHz input signal

The signal source is Audio Precision SYS2522 analog output, balanced GND, 7.699 V pp output, 40 Ω output impedance, high precision mode. The analog input is applied directly to the AD7765’s integrated differential amplifier. The number of FFT samples is 131,072.

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Figure 5. FFT Output for 1 kH Input Signal: Sample Rate 97.65 kSPS, 25 MHz MCLK, 100 μF Reference Star Point Cap, 131,072 Samples Crosstalk

A major performance advantage of implementing simultaneous sampling of multiple channels with discrete ADCs rather than integrated devices is high crosstalk isolation. Table 2 lists the crosstalk between adjacent channels of the AD7765 when a −0.5 dB, 1 kHz input signal is applied to the AD7765 (2).

24-bit, 4-channel, high dynamic range, 156 kSPS per channel simultaneous sampling data acquisition system
Table 2. Crosstalk Performance

Reference voltage configuration
The ADR444 provides the 4.096 V reference voltage for each AD7765 device in this circuit. One of the advantages of the AD7765 is the integrated reference buffer on-chip, which isolates the user from the internal reference sampling circuitry. This means that external buffers are not required when multiple devices share the same reference voltage. The star single-point configuration shown in Figure 6 allows the reference voltage to be applied to each ADC from a single point through parallel lines. This is the best practice to minimize potential interactions between ADCs. The reference voltage is serially tapped to each device from a common reference voltage trace. In addition, an on-chip reference buffer isolates the internal dynamic switched capacitor load from the star point.

Figure 6. Common Variations in Test Conditions for Reference Configurations

The circuit is a scalable design that can be easily adapted by the user to new operating or application conditions.

If only two or three ADC channels are required, the last ADC in the daisy chain can be removed and the SDI of the daisy chain can be simply connected to device (3).

The sampling rate of a single device can be flexibly set to handle different bandwidths. For example, users can connect separate SYNC signals for each channel to daisy-chain into two sets of two channels, or simply use the decimation rate pins to change the effective sampling rate. In this scheme, a pin-compatible device, the AD7764, can also be used, which allows the user to sample at rates up to 312 kSPS in a two-channel daisy-chain configuration.

The Links:   2SB1188T100Q LTM10C210

Related Posts